25 Sep
2019
25 Sep
'19
5:28 a.m.
Module: kamailio
Branch: master
Commit: 517854cba98d33fb632983fe9a2ecf9da9e7e7f9
URL: https://github.com/kamailio/kamailio/commit/517854cba98d33fb632983fe9a2ecf9…
Author: Henning Westerholt <hw(a)skalatan.de>
Committer: Henning Westerholt <hw(a)skalatan.de>
Date: 2019-09-25T11:22:29+02:00
core: enable existing atomic operations for ARMv7 architecture (e.g. newer Rasberry Pi 3)
---
Modified: src/core/atomic/atomic_arm.h
Modified: src/core/atomic/atomic_native.h
Modified: src/core/atomic_ops.h
Modified: src/core/fastlock.h
---
Diff:
https://github.com/kamailio/kamailio/commit/517854cba98d33fb632983fe9a2ecf9…
Patch:
https://github.com/kamailio/kamailio/commit/517854cba98d33fb632983fe9a2ecf9…
---
diff --git a/src/core/atomic/atomic_arm.h b/src/core/atomic/atomic_arm.h
index 2e8f465aa1..98c3f30c46 100644
--- a/src/core/atomic/atomic_arm.h
+++ b/src/core/atomic/atomic_arm.h
@@ -24,7 +24,7 @@
* Config defines:
* - NOSMP
* - __CPU_arm
- * - __CPU_arm6 - armv6 support (supports atomic ops via ldrex/strex)
+ * - __CPU_arm6, __CPU_arm7 - armv6, armv7 support (supports atomic ops via ldrex/strex)
* @ingroup atomic
*/
@@ -61,7 +61,7 @@
#endif /* NOSMP */
-#ifdef __CPU_arm6
+#if defined __CPU_arm6 || defined __CPU_arm7
#define HAVE_ASM_INLINE_ATOMIC_OPS
@@ -387,7 +387,7 @@ inline static long mb_atomic_add_long(volatile long* v, long i)
* -- andrei
*/
-#endif /* __CPU_arm6 */
+#endif /* __CPU_arm6, arm7 */
#endif
diff --git a/src/core/atomic/atomic_native.h b/src/core/atomic/atomic_native.h
index 0edbe5d969..5e83a642ea 100644
--- a/src/core/atomic/atomic_native.h
+++ b/src/core/atomic/atomic_native.h
@@ -30,7 +30,7 @@
* - __CPU_ppc, __CPU_ppc64 - see atomic_ppc.h
* - __CPU_sparc - see atomic_sparc.h
* - __CPU_sparc64, SPARC64_MODE - see atomic_sparc64.h
- * - __CPU_arm, __CPU_arm6 - see atomic_arm.h
+ * - __CPU_arm, __CPU_arm6, __CPU_arm7 - see atomic_arm.h
* - __CPU_alpha - see atomic_alpha.h
* @ingroup atomic
*/
@@ -61,7 +61,7 @@
#include "atomic_sparc.h"
-#elif defined __CPU_arm || defined __CPU_arm6
+#elif defined __CPU_arm || defined __CPU_arm6 || defined __CPU_arm7
#include "atomic_arm.h"
diff --git a/src/core/atomic_ops.h b/src/core/atomic_ops.h
index b757bdceb1..e05e3edb89 100644
--- a/src/core/atomic_ops.h
+++ b/src/core/atomic_ops.h
@@ -157,7 +157,7 @@
* __CPU_ppc, __CPU_ppc64 - see atomic/atomic_ppc.h
* __CPU_sparc - see atomic/atomic_sparc.h
* __CPU_sparc64, SPARC64_MODE - see atomic/atomic_sparc64.h
- * __CPU_arm, __CPU_arm6 - see atomic/atomic_arm.h
+ * __CPU_arm, __CPU_arm6, __CPU_arm7 - see atomic/atomic_arm.h
* __CPU_alpha - see atomic/atomic_alpha.h
*/
/*
diff --git a/src/core/fastlock.h b/src/core/fastlock.h
index a1d1dd80c3..ee95de698b 100644
--- a/src/core/fastlock.h
+++ b/src/core/fastlock.h
@@ -24,7 +24,6 @@
* \ingroup core
* Module: \ref core
* WARNING: the code was not tested on the following architectures:
- * - arm6 (cross-compiles ok, no test)
* - alpha (cross-compiles ok, no test)
* - mips64 (cross-compiles ok)
* - ppc64 (compiles ok)
@@ -74,7 +73,7 @@ typedef volatile int fl_lock_t;
#elif defined(__CPU_sparc)
#define membar_getlock()/* no need for a compiler barrier, already included */
-#elif defined __CPU_arm || defined __CPU_arm6
+#elif defined __CPU_arm || defined __CPU_arm6 || defined __CPU_arm7
#ifndef NOSMP
#warning smp not supported on arm* (no membars), try compiling with -DNOSMP
#endif /* NOSMP */
@@ -189,7 +188,7 @@ inline static int tsl(fl_lock_t* lock)
"swp %0, %2, [%3] \n\t"
: "=&r" (val), "=m"(*lock) : "r"(1), "r"
(lock) : "memory"
);
-#elif defined __CPU_arm6
+#elif defined __CPU_arm6 || defined __CPU_arm7
asm volatile(
" ldrex %0, [%2] \n\t"
" cmp %0, #0 \n\t"
@@ -354,7 +353,7 @@ inline static void release_lock(fl_lock_t* lock)
"stb %%g0, [%1] \n\t"
: "=m"(*lock) : "r" (lock) : "memory"
);
-#elif defined __CPU_arm || defined __CPU_arm6
+#elif defined __CPU_arm || defined __CPU_arm6 || defined __CPU_arm7
#ifndef NOSMP
#warning arm* smp mode not supported (no membars), try compiling with -DNOSMP
#endif